386 motherboard using the UMC UM82C491F chipset © 199? Unknown
The 82C491F was designed to be the sophisticated core for high-end 386DX desktop systems. It moved UMC away from the purely budget-focused designs of the 481-series and introduced more advanced memory and cache orchestration. It is frequently seen on motherboards that were marketed as "386DX/40 Performance Boards."
Role: Northbridge (System Controller).
Cache Management: Integrated logic for Direct-Mapped Write-Through or Write-Back cache. This was the key "performance jump" over the 481 series, allowing the chipset to effectively manage L2 cache latency on faster 386DX-40MHz CPUs.
Memory Controller: Capable of handling significantly tighter memory timings (Interleaved Page Mode). It was known for its ability to accept standard 30-pin SIMMs in diverse configurations without the constant parity-error issues plaguing competing budget chipsets.
System Bus: Primarily ISA-based, but because of its efficient design, it was often the chipset chosen by motherboard manufacturers who wanted to add a VESA Local Bus (VLB) slot to their late-model 386 systems.
Pin Compatibility: The 82C491F was noted for being pin-compatible with some later UMC 486-class chipsets (like the 8491), which made it very popular for manufacturers who wanted to design a single base PCB layout and then decide whether to ship it as a 386 or a 486 board simply by swapping the CPU socket and this Northbridge chip.