386 motherboard using the OPTi 82C381 chipset © 199? Unknown
Developed by OPTi Inc. in the early 1990s, the 82C381 represents the company's early push to decouple performance from pure CPU clock speed by relying heavily on optimized architecture. It is a two-chip core logic set paired with the 82C382 Memory/Cache Controller and traditionally rounded out by a standard 82C206 peripheral controller. This combination allowed 386 systems running at 25MHz or 33MHz to compete directly with early, un-cached 486SX systems.
Core Architecture:
82C381 (System & Bus Controller): Handles the CPU state machine, synchronous clock generation/division, 80387 math coprocessor logic, and real-time data bus conversion (8-bit, 16-bit, and 32-bit cycles).
82C382 (Memory Management Unit): Manages direct-mapped cache operations and orchestrates a flexible Page/Interleave backend memory scheme.
CPU Support: Intel, AMD, and Cyrix 80386DX processors running at 20, 25, and 33 MHz.
Bus Interface: Pure ISA (AT Bus) with software-programmable asynchronous/synchronous clock stretching to guarantee peripheral stability.
Memory Support: Supports page mode or 2-way/4-way interleaving across multiple DRAM banks, maximizing memory bandwidth during cache misses.
Cache Design: Direct-mapped, flexible configuration supporting asynchronous SRAM setups (typically 64KB or 128KB).
The "HiD" Nomenclature: OPTi marketed this chipset under the "HiD" designation, which stood for High-Density/High-Performance Interleaved DRAM. It was one of the first commercially successful chipsets to allow motherboard builders to drop the cost of main memory by utilizing slower, more affordable 80ns DRAM chips without a massive penalty to execution speeds, thanks to its 4-way interleaving controller.
Notable Motherboard Deployments: This combination was the driving force behind notable performance mainboards of the era, such as the Gigabyte GA-386PS and the ubiquitous Chicony CH-386-25D/33A (often silk-screened as the TAM/33-00).
The Single EPROM Feature: To cut production costs for clone manufacturers, the 82C381 data path logic explicitly supported single-chip EPROM BIOS layouts instead of requiring the traditional dual "HI/LO" paired EPROM chips common to older 386 architectures.